The present invention relates to a preamplifier that provides a bias or driving current for an MR head, and more particularly to an open loop biasing circuit for an MR head providing improved common mode rejection, improved power supply rejection, and lower noise.
The electronic storage of data has become a universally accepted and utilized technology in various computer-related industries. A popular method of electronic storage utilizes magnetoresistive (MR) heads to store and recover data on a disk. An MR head employs an MR element that changes in resistivity with changing magnetic flux from data patterns on an adjacent disk surface. Multiple MR heads are employed in separate channels in systems where data is stored on a plurality of disk surfaces. A bias current having a constant value is passed through the MR element, and the change in resistivity is measured by sensing the change in voltage across the MR head. MR heads are extremely sensitive to noise introduced to it from its bias current source. Precise control of the operation of the MR head is necessary to minimize potential errors in storing and recovering data. Preamplifier circuits have traditionally been designed for that purpose.
Design of MR head circuits also has the competing constraint of limited head space to implement preamplifier circuitry. The limited space makes it desirable to share circuits among several MR head channels on an actuator arm or E-block whenever possible. Thus, each individual MR head channel occupies minimal space by not individually including the shared circuitry. The challenge in designing such a system is to share circuitry while preserving the precise operation of each MR head channel to minimize storage and recovery errors. considerations. A good common mode rejection ratio can be achieved by matching the impedances at each terminal of the MR head. A good power supply rejection ratio is provided when the MR head performs consistently despite fluctuations in the power supply of the MR head circuit.
Preamplifiers have taken a variety of forms to attempt to address these performance issues. Circuits have been designed to bias the MR head to control the current therethrough. In one form, a feedback loop adjusts the MR head bias to provide more precise control over the bias current. However, symmetry (and thus common mode rejection) cannot be optimally achieved in a feedback loop configuration. Other circuits have been designed to allow multiplexing of an off-chip capacitor to a plurality of MR head circuits. However, no solution has been developed to allow significant sharing of components by multiple MR head channels, to achieve optimum space implementation, while also providing superior performance characteristics such as good common mode rejection ratio, good power supply rejection ratio, and low noise.